This setting allows for multi-sector transfers, enabled is faster. The IDE HDD Block Mode feature speeds up hard disk access by transferring data from multiple sectors at once instead of using the old single sector transfer mode. When you enable it, the BIOS will automatically detect if your hard disk supports block transfers and configure the proper block transfer settings for it. Up to 64KB of data can be transferred per interrupt with IDE HDD Block Mode enabled. Since virtually all hard disks now support block transfers, there is normally no reason why IDE HDD Block Mode should not be enabled. Although it has been known to cause data corruption in Windows NT.

This BIOS feature speeds up hard disk access by transferring multiple sectors of data per interrupt instead of using the usual single-sector transfer mode. This mode of transferring data is known as block transfers.

When you enable this feature, the BIOS will automatically detect if your hard disk supports block transfers and set the proper block transfer settings for it. Depending on the IDE controller, up to 64KB of data can be transferred per interrupt when block transfers are enabled. Since all current hard disks support block transfers, there is usually no reason why IDE HDD Block Mode should be disabled.

Therefore, you should disable IDE HDD Block Mode only if you actually face the possibility of data corruption (with an unpatched version of Windows NT 4.0). Otherwise, it is highly recommended that you enable this BIOS feature for significantly better hard disk performance!

This feature controls the CPU's access to the PCI bus. If you choose 1 PCI, the CPU will always be granted access right after the current PCI bus master transaction completes, irrespective of how many other PCI bus masters are on the queue. This affords the quickest CPU access to the PCI bus but means poorer performance for the PCI bus devices.

If you choose 2 PCI, the CPU will be granted access after the current and the next PCI transaction completes. In other words, the CPU is guaranteed access after two PCI bus master transactions, irrespective of how many other PCI bus masters are also on the queue. This means the CPU has to wait a little longer than with the 1 PCI option but PCI devices will have quicker access to the PCI bus. If you choose 3 PCI, the CPU will only be granted access to the PCI bus after the current PCI bus master transaction and the following two PCI bus master transactions on the queue have been completed. So, the CPU has to wait for three PCI bus masters to complete their transactions on the PCI bus before it can gain access to the PCI bus itself. This means poorer CPU-to-PCI performance but PCI bus master devices will enjoy better performance.

But irrespective of your choice, the CPU is guaranteed access to the PCI bus after a maximum of 3 PCI master grants. It doesn't matter if there are numerous PCI bus masters on the queue or when the CPU requested access to the PCI bus. It will always be granted access after one PCI bus master transaction (1 PCI), two transactions (2 PCI) or three transactions (3 PCI).

This BIOS feature controls the priority of the processor's accesses to the PCI bus.

If you choose 1 PCI, the processor will always be granted access right after the current PCI bus master completes its transaction, irrespective of how many other PCI bus masters are on the queue. This improves processor-to-PCI performance, at the expense of other PCI transactions.

If you choose 2 PCI, the processor will always be granted access right after the second PCI bus master on the queue completes its transaction. This means the processor has to wait for just two PCI bus masters to complete their transactions on the PCI bus before it can gain access to the PCI bus itself. This means slightly poorer processor-to-PCI performance but PCI bus masters will enjoy slightly better performance.

If you choose 3 PCI, the processor will always be granted access right after the third PCI bus master on the queue completes its transaction. This means the processor has to wait for three PCI bus masters to complete their transactions on the PCI bus before it can gain access to the PCI bus itself. This means poorer processor-to-PCI performance but PCI bus masters will enjoy better performance.

But no matter what you choose, the processor is guaranteed access to the PCI bus after a certain number of PCI bus master grants. It doesn't matter if there are numerous PCI bus masters on the queue or when the processor requests access to the PCI bus. The processor will always be granted access after one PCI bus master transaction (1 PCI), two transactions (2 PCI) or three transactions (3 PCI).

Normally, you should just leave it as auto. This feature allows you to manually set the IRQ for a particular device installed on the AGP and PCI bus. This is especially useful when you are transferring a hard disk from one computer to another; and you don't want to reinstall your OS to redetect the IRQ settings. So, by specifying the IRQ for the devices to fit the original settings, you can circumvent a lot of configuration problems after installing the hard disk in a new system.

Notes :-

If you specify a particular IRQ here, you can't specify the same IRQ for the ISA bus. If you do, you will cause a hardware conflict.

Each PCI slot is capable of activating up to 4 interrupts - INT A, INT B, INT C and INT D

The AGP slot is capable of activating up to 2 interrupts - INT A and INT B

Normally, each slot is allocated INT A. The other interrupts are there as reserves in case the PCI/AGP device requires more than one IRQ or if the IRQ requested has been used up.

The AGP slot and PCI slot #1 share the same IRQs

PCI slot #4 and #5 share the same IRQs

USB uses PIRQ_4

This BIOS feature allows you to manually set the IRQ for a particular device installed on the AGP and PCI buses.

It is especially useful when you are transferring a hard disk from one computer to another; and you don't want to reinstall your operating system to redetect the IRQ settings. By setting the IRQs to fit the original settings, you can circumvent a lot of configuration problems after installing the hard disk in a new system. However, this is only true for non-ACPI systems.

Here are some important notes from the reference motherboard (may vary from motherboard to motherboard) :-

• If you specify a particular IRQ here, you can't specify the same IRQ for the ISA bus. If you do, you will cause a hardware conflict.
• Each PCI slot is capable of activating up to 4 interrupts - INT A, INT B, INT C and INT D.
• The AGP slot is capable of activating up to 2 interrupts - INT A and INT B.
• Normally, each slot is allocated INT A. The other interrupts are reserves and used only when the PCI/AGP device requires more than one IRQ or if the IRQ requested has been used up.
• The AGP slot and PCI slot #1 share the same IRQ.
• PCI slot #4 and #5 share the same IRQs.
• USB uses PIRQ_4.