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Intel Developer Forum 2007 Report
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IDF @ San Francisco Report

The Intel Developer Forum is currently underway at San Francisco, from September 18-20. Let's take a look at some of the latest news from the forum.



Rapid Technology Cadence
- 45nm high-k metal gate
- USB 3.0
- Intel QuickAssist Technology
- The Tolapai chip
- McCreary and Danbury technologies

Patrick Gelsinger
Senior Vice President and General Manager,
Intel Digital Enterprise Group

32nm, Penryn & Nehalem
- SilverThorne 45nm processors
- Montevina mobile platform

Paul Otellini
Intel Corporation President and CEO

Breaking the Barriers to Mobility
- Santa Rosa refresh
- Future mobile roadmap
- WiFi-N & WiMAX

David (Dadi) Perlmutter
Senior Vice President and General Manager,
Intel Mobility Group

Unleashing the Internet Experience
- The Menlow 45nm platform
- The Moorestown SOC platform

Anand Chandrasekher
Senior Vice President and General Manager,
Intel Ultra Mobility Group


Gelsinger Speaks On Rapid Technology Cadence

Showing off a 45nm Nehalem wafer are Pat Gelsinger, senior vice-president and general manager Digital Enterprise Group, and Jim Brayton, Intel Nehalem project manager.

Patrick Gelsinger, senior vice president and general manager of Intel’s Digital Enterprise Group, gave a variety of updates on Intel's work with the industry on the company’s processors, surrounding technologies and "tick-tock" design cadence, including new details on Intel's upcoming 45 nanometer (nm) products. He also discussed the industry's recent moves in energy efficient computing, virtualization, broad range of software enabling, as well as recent system architecture initiatives spanning the popular USB interconnect to upcoming lead-free products for the company’s Intel® vPro™ desktop PCs.

During his speech, Gelsinger showed the first-ever Intel 45nm High-k metal gate next-generation microarchitecture (Nehalem) dual processor server that uses the element Hafnium instead of silicon in portions of the 700 million-plus transistors inside the processor die, which is about the size of a postage stamp. Nehalem is the codename of a new processor microarchitecture arriving in 2008 that will provide up to three times the peak memory bandwidth of current competing processors. He also showed broad industry support for the Intel® QuickPath Architecture. The QuickPath Interconnect provides high-speed data paths to Nehalem’s processor cores.

In addition to compute performance and memory bandwidth, Intel continues to provide leadership in I/O when Gelsinger announced the formation of the USB 3.0 Promoter Group. This revolutionary architecture will use a single connector and cable delivering over 10 times the performance of USB 2.0 while preserving backwards compatibility to more than 2 billion existing USB devices.

Along with Intel, the promoter group has been formed with HP, NEC Corporation, NXP Semiconductors, Microsoft, and Texas Instruments Incorporated. USB 3.0 will be the first I/O interface to include support for both optical and copper interconnects, scalable protocol, and energy efficiency optimizations for use in the PC, consumer electronics, and mobile segments.

Gelsinger reviewed Intel’s QuickAssist Technology and its escalation of industry product development. QuickAssist Technology, first disclosed at the IDF in Beijing in April, is Intel's suite of hardware and software technologies addressing the unique requirements of accelerators in enterprise platforms. He reviewed the first Intel device to include the Intel® QuickAssist Integrated Accelerator for cryptography, codenamed Tolapai. 

With availability targeted for 2008, Tolapai – a system on a chip – will deliver significant improvements in power-efficient performance and form factor with up to eight times the IP Security throughput, up to 20 percent reduction in power, and up to a 45 percent smaller footprint over previous multi-component security solutions in embedded and communications market segments.

On the heels of the latest-generation roll-out of Intel vPro processor technology, Gelsinger revealed plans to further evolve security and PC management benefits through the 2008 product codenamed McCreary. McCreary will include new halogen and lead-free 45nm dual and quad-core processors, a new chipset codenamed Eaglelake, an integrated Trusted Platform Module (TPM) and a more secure, manageable data encryption solution codenamed Danbury. 

Danbury technology builds data encryption and decryption directly into the hardware providing greater protection of encryption keys and allows much simpler system management and key recovery. Intel Active Management technology also enables these operations to occur in “out-of-band” environments, meaning even if the OS is down or inoperable.

Gelsinger pointed to a wall of computer systems that Intel will deliver to suit most users’ computing and cost needs. He showed how customers, such as Paradigm, will use Intel Xeon®-based workstations with a new 1600MHz front side bus and Intel software tools to solve scientific problems, such as oil and gas exploration. Mark Barrenechea, president and chief executive officer of Rackable Systems, discussed Rackable's ICE Cube* Modular Data Center on Wheels, which has 1400 quad core Intel Xeon servers in a single 40-foot truck container.

Gelsinger also discussed the improvements that solid state disk technology can bring to enterprise server and storage technology for IA platforms. He announced that products delivering substantial improvements in read performance and power savings from Intel utilizing non-volatile memory technology will be available next year.

Gelsinger shared his vision for I/O consolidation on Ethernet and steps to get to a converged network that supports both Fibre Channel over Ethernet (FCoE) and local area networks. In support of this vision, he announced availability of  Intel® 82598 10 Gigabit Ethernet Controller now with full support for FCoE solution stack coming in 2008.

Next Page : Otellini Speaks On 32nm, Penryn & Nehalem >>>


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