PCI Pipelining
Common Options : Enabled, Disabled
Quick Review
This BIOS feature determines if PCI transactions to the memory subsystem will be pipelined.
If the PCI pipeline feature is enabled, the memory controller allows PCI transactions to be pipelined. This masks the latency of each PCI transaction and improves the efficiency of the PCI bus.
If the PCI pipeline feature is disabled, the memory controller is forced to check for outstanding transactions from other devices to the same block address that each PCI transaction is targeting.
For better PCI performance, the PCI pipeline should be enabled. This allows the latency of the bus to be masked for consecutive transactions.
However, if your system constantly locks up for no apparent reason, try disabling this feature. Disabling PCI Pipelining reduces performance but ensures that data coherency is strictly maintained for maximum reliability.
Support Tech ARP!
If you like our work, you can help support out work by visiting our sponsors, participate in the Tech ARP Forums, or even donate to our fund. Any help you can render is greatly appreciated!
Click here to find out how you can do that now!
Links: Discuss BIOS options here in our forums | Back to the list of BIOS options