2T Command

Common Options : Enabled, Disabled, Auto

Quick Review

This BIOS feature allows you to select the delay between the assertion of the Chip Select signal till the time the memory controller starts sending commands to the memory bank. The lower the value, the sooner the memory controller can send commands out to the activated memory bank.

When this feature is disabled, the memory controller will only insert a command delay of one clock cycle or 1T.

When this feature is enabled, the memory controller will insert a command delay of two clock cycles or 2T.

The Auto option allows the memory controller to use the memory module's SPD value for command delay.

If the SDRAM command delay is too long, it can reduce performance by unnecessarily preventing the memory controller from issuing the commands sooner.

However, if the SDRAM command delay is too short, the memory controller may not be able to translate the addresses in time and the "bad commands" that result will cause data loss and corruption.

It is recommended that you try disabling 2T Command for better memory performance. But if you face stability issues, enable this BIOS feature.

Support Tech ARP!

If you like our work, you can help support out work by visiting our sponsors, participate in the Tech ARP Forums, or even donate to our fund. Any help you can render is greatly appreciated!