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Adjacent Cache Line Prefetch

Common Options : Enabled, Disabled

Quick Review

The processor has a hardware adjacent cache line prefetch mechanism that automatically fetches an extra 64-byte cache line whenever the processor requests for a 64-byte cache line. This reduces cache latency by making the next cache line immediately available if the processor requires it as well.

When enabled, the processor will retrieve the currently requested cache line, as well as the subsequent cache line.

When disabled, the processor will only retrieve the currently requested cache line.

In a desktop system, enabling this feature improves performance as there's a high probability of the processor requiring the next cache line as well as the currently requested cache line. It is therefore recommended that you enable this BIOS feature in a desktop system.

But in a server, the probability of the next cache line being required by the processor is lower than that of a desktop system. The higher cache miss ratio inevitably leads to higher bus utilization, which reduces the processor's performance.

You will need to evaluate the performance effect of this feature on your server and determine if it should be disabled or enabled for better performance. But servers should generally disable this feature.

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