2T Gain-Cell DRAM - Future Of Larger, Cheaper Processor Cache?

With multi-core processors becoming ubiquitous, memory bandwidth will become more and more of an issue as multiple processing cores have to fight for the same resource. Adding fast on-die SRAM memory is one way to improve memory bandwidth. However, it is very costly in the number of transistors and die area it requires, as each SRAM cell requires 6 transistors to build. Commodity DRAM, used for main memory, is much denser but also a lot slower. It also cannot be integrated into the CPU die due to the differences in manufacturing process.

To increase the amount of on-die memory, a cheaper memory technology (in terms of chip real estate) was needed. To this end, Intel developed a new category of DRAM memory, called 2T Gain-Cell Memory. Unlike commodity DRAM, this type of DRAM is built using standard microprocessor technology and is designed to provide a new choice of fast on-chip memory.

The 2T gain-cell memory has a 2ns access time and can sustain 8-cycle successive accesses to the same memory bank. This allows it to deliver 128 GB/s of bandwidth when it runs at 2 GHz. This is much faster than what commodity DRAM is capable of. Even the Tukwila processor's four DDR3 memory channels is only capable of attaining a total peak memory bandwidth of 34 GB/s.

More importantly though, the new 2T gain-cell memory can be built using just two transistors per cell. This reduces the size of each cell, effectively doubling its memory density when compared to SRAM. In other words, you can fit twice as much 2T gain-cell memory cells as regular SRAM cells.

However, this is not a replacement for commodity DRAM. Commodity DRAM uses devices separate from a microprocessor or chipset, and built using technology specific to that type of memory. This type of memory can only be used for on-chip caches. Currently, the form of pipelining used by Intel makes it especially useful in applications like the tag ram. The tag ram is a part of the cache design that is used to determine whether a particular piece of data is in the cache or not.

In addition, Intel asserts that this is merely a research prototype. There is currenly no plan to put this into any particular product. The prototype, however, had demonstrated the benefits of the technology, and the feasibility of putting this type of memory in production should Intel decide to do so in the future.

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