P-States In Multi-Core Processors

Just like processor C-states, multi-core processor P-states are tricky. Each core can request different P-states, but the final P-state in each core varies. It all depends on the efficiency of the processor power control unit.

Single Core

The core P-state is always the same as the processor P-state.

Dual Core

The processor P-state is equivalent to the highest P-state of the two cores. Since the Core 2 Extreme X6800 clock ratio/voltage table was shown in previous page, we will use that CPU as an example.

Let's say you are running SuperPI in Core 1, and WinAmp only using Core 2. Core 1 should be running at its highest working state (P0), while Core 2 should be running at its lowest working state (P5).

The final clock speed and vcore will be 2.93 GHz and 1.2875 V, because the Core 2 Extreme only has a single PLL (clock source) and one Vcore (voltage source).

If Core 1 follows the Core 2's P-state, your SuperPI will be running very slowly. The AMD Athlon 64 X2 processor also has a single PLL and one Vcore. Hence, the scenario is exactly the same like that of the Core 2 Extreme X6800.

Quad Core (Intel)

The Kentsfield processor is made up of two Conroe chips placed side by side. The first Conroe chip (Cores 1 & 2) is referred as Site 1, and the second Conroe chip (Cores 3 & 4) is referred as Site 2. Each site has its own PLL source but both sites shared the same Vcore.

Let's say we have a Core 2 Extreme QX6700 with the following clock ratio/ voltage table :

If you refer to the diagram on the left, Site 1 will be running at P0, while Site 2 will be running at P1. Hence, Cores 1 and 2 will be running at 2.67 GHz while Cores 3 and 4 will be running at 2.13 GHz. All cores share the same Vcore (1.2875 V) because Site 1 has a higher P-state than Site 2, and only one voltage source is available.

Quad Core (AMD)

AMD's next-generation monolithic quad-core processor (Barcelona) has an advanced P-state management technique, compared to current processors. ikanayam lets us in on some Barcelona power management secrets :

There are a total of 3 power planes in Barcelona – one for the processing cores (all 4 cores shared a single power plane), one for the north bridge (including IMC and cache) and the last one one for I/O. However, each core has its own PLL, so they can step into different discrete frequencies independent of each other.

In addition, there is also a separate PLL for the non-core components (like the north bridge, cache, HTT bus, etc.) which don’t execute instructions. The non-core clock can scale down when external bus activity is low, and vice versa. I'll update this part with more details when Barcelona is out in the market.