PCI Chaining

Common Options : Enabled, Disabled

Quick Review

This BIOS feature is designed to speed up writes from the processor to the PCI bus by allowing write combining to occur at the PCI interface.

When PCI chaining is enabled, up to four quadwords of processor writes to contiguous PCI addresses will be chained together and written to the PCI bus as a single PCI burst write.

When PCI chaining is disabled, each processor write to the PCI bus will be handled as separate non-burstable writes.

Needless to say, writing four quadwords of data in a single PCI write is much faster than doing so in four separate non-burstable writes. A single PCI burst write will also reduce the amount of time the processor has to wait while writing to the PCI bus.

Therefore, it is recommended that you enable this feature for better CPU to PCI write performance.

Support Tech ARP!

If you like our work, you can help support out work by visiting our sponsors, participate in the Tech ARP Forums, or even donate to our fund. Any help you can render is greatly appreciated!