Super Bypass Wait State

Common Options : 0 Cycle, 1 Cycle

Quick Review

This BIOS feature is used to fine-tune the Super Bypass feature to correct for internal timing variations.

When set to 0 Cycle, the memory controller initiates all super bypass requests without delay.

When set to 1 Cycle, the memory controller forces a wait state delay for all super bypass requests.

Official documents recommend that a wait state be added for a 133 MHz (266 MHz DDR) memory bus. Systems using a 100 MHz (200 MHz DDR) memory bus do not need this delay.

Forcing a wait state on all super bypass requests reduces the effectiveness of the Super Bypass feature. Therefore, it is recommended that you try using the 0 Cycle setting for maximum performance.

However, if you experience system stability issues after using this 0 Cycle setting, set this feature to 1 Cycle. This slows down super bypass transactions but will allow your system to use the Super Bypass feature at higher clock speeds.

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