PCI Master 0 WS Read
Common Options : Enabled, Disabled
Quick Review
This BIOS feature determines whether the chipset inserts a delay before any reads from the PCI bus.
If PCI Master 0 WS Read is enabled, read requests to the PCI bus are executed immediately (with zero wait states), if the PCI bus is ready to send data.
If PCI Master 0 WS Read is disabled, every read request to the PCI bus will be delayed by one wait state.
It is recommended that you enable this feature for better PCI read performance.
However, disabling it may be useful if you are attempting to stabilize an overclocked PCI bus. The delay will generally improve the overclockability and stability of the PCI bus.
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