PCI Target Latency

Common Options : Enabled, Disabled

Quick Review

This BIOS feature determines if the system controller should conform to the PCI maximum target latency rule.

When this feature is enabled, the system controller will disconnect the PCI bus master when it cannot service a read request within 32 PCI clock cycles for the initial read and 8 PCI clock cycles for subsequent reads. The PCI bus master will then rearbitrate for access to the PCI bus.

When this feature is disabled, the PCI bus master will not be disconnected when it cannot service a read request within the stipulated 32 PCI clock cycles for the initial read and 8 PCI clock cycles for subsequent reads. The PCI bus master is allowed to complete with its transactions.

It is recommended that you enable this feature to enforce the PCI maximum target latency rule and prevent potential deadlocks.

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